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MT46V32M16P-5B IT:J

Name: Micron Technology MT46V32M16P-5B IT:J
Brand: Micron
SKU: 340-122535-TRAY
Price: 16.73 SGD
Availability: OutOfStock

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Mouser No:

340-122535-TRAY

Mfr. No:

MT46V32M16P-5B IT:J

Mfr.:

Micron

Description:

DRAM DDR 512Mbit 16 66/66TSOP 1 IT

Lifecycle:

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Lifecycle information is unclear. Obtain a quote to verify the availability of this part number from the manufacturer.

Datasheet:

MT46V32M16P-5B IT:J Datasheet (PDF)

ECAD Model:

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Learn more about Micron MT46V32M16P-5B IT:J

Availability

Stock:: Non-Stocked

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Factory Lead Time:: 53 Weeks Estimated factory production time.

Long lead time reported on this product.

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Ext. Price:

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Pricing (SGD)

Qty.	Unit Price	Ext. Price
	$16.73	$16.73

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Micron Technology
Product Category:	DRAM
RoHS:
Type:	SDRAM - DDR
Memory Size:	512 Mbit
Data Bus Width:	16 bit
Maximum Clock Frequency:	200 MHz
Package/Case:	TSOP-66
Organisation:	32 M x 16
Access Time:	700 ps
Supply Voltage - Min:	2.5 V
Supply Voltage - Max:	2.7 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Series:	MT46V
Packaging:	Tray
Brand:	Micron
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	TW
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	1080
Subcategory:	Memory & Data Storage
Supply Current - Max:	85 mA
Unit Weight:	10.717 g

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Filter Document:

Datasheet

MT46V32M16P-5B IT:J Datasheet (PDF)

PCN

DDR x16/x8, SDRAM x32/x16 TSOP Package Internal Leadframe Design/Structure Change (PDF)

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CNHTS:: 8542329010
CAHTS:: 8542320020
USHTS:: 8542320028
MXHTS:: 8542320299
ECCN:: EAR99

DDR SDRAM

Micron DDR SDRAM is revolutionary and pioneering technology that allows applications to transfer data on the rising and falling edges of a clock signal. This doubles bandwidth and improves performance over SDR SDRAM. To achieve this functionality, Micron uses a 2n-prefetch architecture where the internal data bus is double the size of the external data bus, so data capture can happen two times each clock cycle.